A NOR circuit of the kind that might be implemented in gallium arsenide using enhancement mode and depletion mode MESFET (metal semiconductor field effect transistor) technology is shown at 10 in FIG. 1 of the accompanying drawings. The NOR circuit comprises enhancement-mode MESFETs (EFETs) 14 and 16, which receive input logical signals A and B at their respective gates, have their sources connected to the negative supply V.sub.ss and have their drains connected to a node 20, and a depletion-mode MESFET (DFET) 18 that has its drain connected to the positive supply V.sub.dd and its gate and source connected to the node 20. The DFET 18 serves as a current source. It will be understood by those skilled in the art that the signal at the node 20 represents the logical operation A NOR B. Normally, the signal at the node 20 would be applied as an input to another logic circuit, such as the inverter shown in FIG. 1 at 12. The inverter 12 is of conventional form and comprises an EFET 22 and a DFET 24.
In an implementation of the circuit shown in FIG. 1 in monolithic integrated form using gallium arsenide as the substrate material, the positive supply V.sub.dd may be at about 1.5 to 2.5 volts above the negative supply V.sub.ss, and the voltage levels , relative to the negative supply V.sub.ss, corresponding to logical 0 and logical 1, referred to hereinafter as voltage output low (VOL) and voltage output high (VOH) might be 0.1 and 0.7 volts. The threshold value V.sub.th for the gate-to-source voltage V.sub.gs for the EFETs 14, 16 and 22 might be about 0.25 to 0.4 volts. Therefore, in order to place the EFET 22 reliably in its conductive state, and bring the drain of the EFET 22 to its VOL level, the voltage at the node 20 must exceed the voltage at the source of the transistor 22 by at least 0.4 volts, i.e. V.sub.gs for the transistor 22 must be at least 0.4 volts. Ideally, V.sub.ss for all the transistors is the same, and if VOH for the transistor 16 is 0.7 volts, then V.sub.gs for the transistor 22 will exceed V.sub.th by a noise margin of about 0.3 volts and be sufficient to place that transistor reliably in its conductive state. Unfortunately, however, owing to the finite resistance of the conductor runs in an integrated circuit chip, V.sub.ss is not generally the same for all the transistors. The variation in V.sub.ss among the transistors might be such that V.sub.ss for the transistor 16 could exceed V.sub.ss for the transistor 22 by as much as 0.3 volts. It will then be understood that if VOL for the transistor 16 is 0.1 volts above V.sub.ss for that transistor, V.sub.gs for the transistor 22 might equal or exceed V.sub.th, and consequently the transistor 22 might be placed in its conductive state when it should in fact be placed in its non-conductive state. In order to place the transistor 22 reliably in its non-conductive state when the node 20 is at the VOL level, the VOL level should be brought closer to V.sub.ss so as to increase the noise margin.